Integrated circuit (IC) devices include various generic structures and logic blocks that can be configured to perform any of a variety of tasks and functions. Some of these logic blocks include logic circuitry, registers, I/O blocks, embedded memory blocks, etc., that are programmable to support a wide array of user applications. For instance, I/O blocks in an IC device can be configured to support different protocols and embedded memory blocks in the IC device are used as buffers to support these different protocols.
Generally speaking, embedded memory blocks in an IC device usually have a predetermined number of memory bits. However, different I/O protocols require buffers in different sizes. Some protocols or systems require deep buffers while others require only shallow buffers. Generally, systems that require shallow buffers may perform faster than systems that require deep buffers. In other words, systems that require fewer memory bits can have a higher operating speed compared to systems that require more memory bits.
However, embedded memory blocks with a fixed number of memory bits have a fixed read and write access time. Consequently, embedded memory blocks that have a fixed number of memory bits may not operate at a higher speed even though only a portion of the available memory bits are used. For example, a high speed serial connection protocol, e.g., Peripheral Component Interconnect Express (PCIe), that have varying operating speeds may be constrained by the maximum read access time of the memory blocks in the device. In other words, memory blocks with a fixed number of memory bits have a fixed access time.
Therefore, it is desirable to have embedded memory blocks with variable buffer depth so that the memory blocks may be configured based on the requirements of the various protocols used in the system. It is within this context that the invention arises.